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| www.fairchildsemi.com TMB22153AMS100 Demonstration Board for the TMC22x5yA Multistandard Digital Video Decoder Features * * * * * Accepts analog composite or YC Outputs 10-bit digital RGB, D1, or YCBCR Locks to studio reference R-bus serial interface compatibility Raytheon demo board compatibility Description The TMB22153AMS100 Demonstration Board showcases the TMC22x5yA Digital Video Decoder. The onboard MMC FE-100 dual 10-bit A/D modules generate digitized composite or YC for the decoder. The decoder outputs D1, digital RGB, or YCBCR. Clocks and synchronization pulses are generated by Fairchild's TMC2072 Genlocking Video Digitizer. Preliminary Information Applications * * * * Evaluation of TMC22x5yA Digital Video Decoder Input for Genesis 10-bit Line Doubler board Input for DAC and encoder demo boards System Breadboarding Related Products * * * * * TMC2069P7C DAC demonstration board TMC2074P7C Encoder demonstration board TMB2193MS100 Encoder demonstration board TMC2070P7C R-bus interface board Raydemo software Block Diagram Analog signals D.C. supply RBUS FE-100x-1 TMC2072 Digital signals 96 way Edge Connector (male) Composite/Luma video input Micro (top) FPGA (bottom) Y/C video input FE-100x-2 Chroma video input TMC22153A Framestore Connector TMB22153AMS100 SW1 10 bit G/Y 10 bit B/U 10 bit R/V or D1 PXCK clock HSYNC VSYNC SYNC\ (D/A signals) BLANK\ (D/A signals) Rev. 001 PRELIMINARY INFORMATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. They may change without notice. Contact Fairchild Semiconductor for current information. TMB22153AMS100 PRELIMINARY INFORMATION Functional Description The TMB22153AMS100 is designed to demonstrate the performance of the TMC22x5yA Digital Video Decoder. For complete descriptions of the TMC22x5yA, TMC2072, TMC1185, and TMC2242 please refer to part datasheets. The TMB22153AMS100 is designed to be used in conjunction with other Fairchild demo boards, namely the TMC2069P7C DAC, and TMB2193MS100 encoder boards. The 96 pin edge connectors plug easily into each other. When used together, the boards demonstrate a high performance 10-bit digital video decoding system. TMC2072 Genlocking Video Digitizer The TMC2072 Genlocking Video Digitizer accepts analog composite data through the composite input BNC on the left side of the board. A 20MHz clock crystal provides the Genlock with an input clock. The TMC2072 outputs horizontal and vertical syncs, and a 27MHz clock. The clock is used to drive the Decoder and EPLD. Like the TMC22x5yA, the Genlock part must be programmed at startup. Instructions on how to do this are in the "Microcontroller" section of this documentation. EPLD An Altera EPF10K10TC144-4 EPLD executes several essential board functions. The EPLD serves as a buffer and multiplexer for data buses and a register for several important control signals. These signals may be cross-referenced to the included schematics. The EPLD control registers may be modified using the Raydemo software. The Raydemo EPLD R-bus address is 0000001. For a more complete description or specification of signals going to or coming from the TMC22x5yA and TMC2072, please refer to the Fairchild Semiconductor Data Book (also available on CDROM) or the website at www.fairchildsemi.com. TMC22x5yA Digital Video Decoder Preliminary Information The TMC22x5yA accepts digitized video input on two 10-bit buses, "YOVER[9:0]" and "COVER[9:0]". Based on the status of its control registers, it then outputs the data to the output edge connector of the board in a variety of formats. Please see Table 1 for a listing of board default video standards and output formats that are loadable to the control registers. After the TMC22x5yA control registers have been initially loaded by the microcontroller, subsequent changes to the control registers may be made through the R-bus interface and Raydemo software. It is important that the control registers be loaded correctly in order to obtain the desired output. Once the control registers have been set to output the correct data from the TMC22x5yA, then several board switches must also be correctly configured in order to obtain the desired output. Microcontroller An Atmel 89C55 microcontroller is used to program the TMC22x5yA and TMC2072 registers. The microcontroller programs the parts through the R-bus at power up and reprograms them each time the "Reset" button is pushed. Please see Table 1 on the next page for a description of available microcontroller-programmed board configurations. Table 1. TMB22153AMS100 Demonstration Board Video Standard Selection P3-0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Input Format composite Y/C composite Y/C composite composite, field-based composite, field-based composite, frame-based composite Y/C composite Y/C composite composite, field-based composite, field-based reserved Video Standard NTSC NTSC NTSC NTSC NTSC NTSC NTSC NTSC PAL PAL PAL PAL PAL PAL PAL Output Format YUV YUV D1 D1 RGB YUV D1 YUV YUV YUV D1 D1 RGB YUV D1 2 PRELIMINARY INFORMATION TMB22153AMS100 Quick Setup/Verification for Composite NTSC Input, YUV Output 1. Configure jumpers: If using R-Bus interface, JP2 must be closed (connected) Leave JP1 open (unconnected) Verify that JP4 is linked to the odd-numbered pins of JP6 2. Configure slider-switches (push red slider TOWARD specified marking on board) : E1 E2 E3 E4 E5 E6 E7 E8 3. "FPGA" "FPGA" "VS" "PXCK4\" "GP" "GH" "GV" "XP" 4. 5. 6. Ensure BNC J1 (VIN1) is connected to composite NTSC signal. Ensure piano-key switches P3-0, Y are in the "LOW" (down) position. Plug in power-supply connector and apply power. LED's corresponding to applied voltages should lightup. Press and release the MRST button (S2). The TMC2072 and TMC22x5yA should both be programmed. To verify the TMC2072 is functioning correctly, check for presence of a clock (TP sync pulses, VS (TP18) and HS (TP17). Likewise, to verify the TMC22x5yA is functioning, check for presence of DHSYNC (TP5) and DVSYNC (TP6). 7. Preliminary Information Power Supply Requirements The TMB22153AMS100 power supply connector is on the top edge of the board toward the left side. The TMB22153AMS100 board requires DC power supply voltages of +5V and -5V. The +5V supply provides power and voltage references to the TMC22x5yA and /TMC2072, as well as driving TTL logic devices. It is for this reason that a bench power supply with short cable lengths is recommended. If you have reason to believe the bottom cover has been removed, remove it and configure S4 as follows: 1-7 8 ON (low) OFF (high) 3 Preliminary Information CKDRIVE FSIN_CLK ADCLK1 ADCLK2 DICECLK DECODER GY[0..9] BU[0..9] YOVER[0..9] RV[0..9] COVER[0..9] GENLOCK DHSYNC GRST\ GRST AN COMP/LUMA GHSYNC GVSYNC DECCLK SDA SCL SDA SCL GPXCK FID_0 FID_0 HREF CREF FSET VALID DRST\ DRST DCSB DA1 SA0 DA0 SA1 MPU[0..7] SA2 DRW SDA SCL DECODER GY[0..9] BU[0..9] RV[0..9] OP-CONN SIGNAL HEADER Y[0..9] GY[0..9] BU[0..9] RV[0..9] MPU[0..4] FRAMESTORE CONNECTOR YOVER[0..9] HS VS SCL SDA FSIN_CLK RESET\ YOVER[0..9] HS VS SCL SDA COVER[0..9] FSIN_CLK RESET COVER[0..9] OHS OVS SCL SDA BLANK\(DAC) RESET\ OHS OVS SCL SDA BLANK(DAC) RESET Y[0..9] SA0 SA1 SA2 DCSB GENLOCK DA1 DA0 CVBS[0..7] MPU[0..7] DRW SDA SCL SDA SCL COVER[0..9] YOVER[0..9] MPU[0..7] OHS OVS BUFFER MASTER0 MASTER1 FPGA COVER[0..9] YOVER[0..9] MPU[0..7] SWW SWW HS VS DHSYNC DVSYNC BUFFER MASTER0 MASTER1 HS VS DHSYNC DVSYNC OHS OVS VALID SWW FSET SWW VALID VREF GPXCK BUFFER MASTER0 MASTER1 SA0 SA1 SA2 BUFFER MASTER0 MASTER1 GHSYNC GVSYNC DECCLK AVOUT AVOUT SCL SDA BLANK\(DAC) RESET\ DICECLK CVBS[0..7] AN COMP/LUMA HS VS HS VS DVSYNC DVSYNC OHS OVS DHSYNC Y[0..9] OHS OVS SCL SDA BLANK(DAC) RESET DICECLK FID_0 HREF CREF VALID VREF IXPXCK 675MHZ IXHSYNC\ IXVSYNC\ 135MHZ IXHSYNC IXVSYNC IXPXCK NTSC/PAL PGM_OUT RGB D1 NTSC/PAL PGM_OUT RGB D1 675MHZ 135MHZ RV[0..9] Y[0..9] RV[0..9] BU[0..9] BU[0..9] GY[0..9] EDGE CONNECTOR IXPXCK IXHSYNC\ IXVSYNC\ GPXCK GHSYNC GVSYNC IXPXCK IXHSYNC IXVSYNC GPXCK GHSYNC GVSYNC CKDRIVE FSIN_CLK ADCLK1 ADCLK2 DICECLK DECCLK HS VS 4 SA0 SA1 SA2 SDA SCL AVOUT AVOUT DCSB DA1 DA0 DRW YOE10 COE10 DCSB DA1 DA0 DRW YOE10 COE10 DECCLK DECCLK 675MHZ PGM_OUT CLAMP RGB BLANK(DAC) NTSC/PAL D1 CVBS[0..7] PGM_START PGM_START HREF CREF VREF FSET FPGA 675MHZ D1ENFS FSOE FSER D1ENFS FSOE FSER PGM_OUT CLAMP RGB BLANK\(DAC) NTSC/PAL D1 HREF CREF VREF FSET POWER POWER FSOE FSER D1ENFS FSOE FSER IXPXCK IXHSYNC IXVSYNC FRAMESTORE CONNECTOR OP-CONN IXPXCK IXHSYNC\ IXVSYNC\ FID_0 HREF CREF VALID VREF NTSC/PAL PGM_OUT RGB D1 FID_0 HREF CREF VALID VREF NTSC/PAL PGM_OUT RGB D1 SMA MODULES TMB22153AMS100 ADCLK1 ADCLK2 ADCLK1 ADCLK2 YOVER[0..9] YOVER[0..9] CLAMP COVER[0..9] COVER[0..9] CLAMP YOE10 YOE10 COE10 COE10 AN COMP/LUMA AN COMP/LUMA SMA MODULES MCU 135MHZ 135MHZ PGM_OUT PGM_START PGM_OUT PGM_START DRST GRST DRST\ GRST\ RESET\ RESET SDA SCL SDA SCL MCU PRELIMINARY INFORMATION VCC TP1 TP C1 0.1uF C11 + 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C2 C3 C4 C5 C6 C7 C8 C9 C10 AN COMP/LUMA 22uF/6.3v U1 PRELIMINARY INFORMATION R1 75 22uF/6.3v + NC NC NC NC NC NC CVBS[0..7] 99 85 84 83 80 79 GPXCK GHSYNC GVSYNC CVBS[0..7] GPXCK GHSYNC GVSYNC VALID 9 10 11 12 13 14 15 19 20 43 47 NC NC NC NC NC NC NC NC NC NC NC VIN1 VIN2 VIN3 RESET 32 GHSYNC 33 GVSYNC GHSYNC GVSYNC 1 H1 H2 C12 0.1uF 1 CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 21 22 23 24 25 28 29 30 CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 65 61 58 7 4 5 SDA SCL 17 INT 34 VALID 40 LDV 88 COMP 70 VREF 68 RT 57 RB C13 6.8pF GPXCK L1 BURL 31 C17 35 FID0 36 FID1 37 FID2 0.1uF C18 0.1uF INDUCTOR C19 150pF C20 390pF C8 NOT INSTALLED IF CR10 IS INSTALLED C14 0.1uF C15 0.1uF C16 0.1uF 1 CR1 1.235V 2 DDS OUT CBYP PFD IN PXCK 82 75 77 45 VCC 1 2 3 SA0 SA1 SA2 86 94 91 93 PXCK SEL EXT PXCK CLK IN CLK OUT VCC VCC R2 75 R3 75 R4 3.3K Preliminary Information 5 H3 1 53 54 56 59 62 66 71 76 78 NC NC NC NC NC NC NC NC NC TMC2072KHC TP2 TP DGND AGND GND TP3 TP TP4 TP TP5 TP R5 4.75K R6 4.75K GRST\ GRST\ VCC Y1 C21 OUT 5 20MCLK 0.1uF 20MHz SDA SCL SDA SCL TMB22153AMS100 SA0 SA1 SA2 SA0 SA1 SA2 Preliminary Information 6 VCC MPU[0..7] R37 1K 77 76 35 74 MSEL0 MSEL1 nSTATUS nCONFIG DCLK CONF_DONE INIT_DONE H12 TP21 TP22 TP23 TP24 TP25 TP TP TP TP TP TP 107 2 14 U9 3 4 OE nCS D1ENFS 6 DCLK nCASC EPC1PC8 CREF DATA 2 1 1K 1K 1K U2 R38 R39 R40 TP29 TP TP30 TP TP31 TP YOVER[0..9] COVER[0..9] MPU[0..7] YOVER[0..9] COVER[0..9] BUFFER MASTER0 MASTER1 BUFFER MASTER0 MASTER1 TP26 TP27 TP28 TP TP BLANK\(DAC) NTSC/PAL RGB D1 BLANK\(DAC) NTSC/PAL RGB D1 DECODER PARALLEL INTERFACE H4 H6 H7 1 1 1 DCSB DA1 DA0 106 3 142 141 144 143 11 7 nCE nCEO nW S nRS nCS CS RDYnBSY CLKUSR H11 1 116 114 113 112 111 110 109 108 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 TDI TDO TCLK TMS 105 4 1 34 54 56 124 126 DEDIN DEDIN DEDIN DEDIN GCLK0 GCLK1 DEV_CLRn DEV_OE DECCLK 125 55 122 128 H9 1 GRAB PIXEL_GRAB LINE_GRAB PGM_OUT BLANK\(DAC) SDA SCL D1 RGB 1 NTSC/PAL VREF HREF OHS OVS MPU7 MPU6 MPU5 MPU4 MPU3 MPU2 MPU1 MPU0 AVOUT DHSYNC DVSYNC MASTER1 MASTER0 PGM_START YOVER9 YOVER8 YOVER7 YOVER6 YOVER5 YOVER4 YOVER3 YOVER2 YOVER1 YOVER0 COVER9 COVER8 COVER7 COVER6 COVER5 COVER4 COVER3 COVER2 COVER1 COVER0 DRW SWW FSET TP6 TP DCSB DA1 DA0 1 1 H10 H5 TP7 TP TP8 TP TP9 TP FSET OHS OVS FSER YOE10 COE10 D1ENFS HREF CREF VREF FSOE COE10 YOE10 CLAMP FSOE DRW CLAMP EPF10K10TC144 FSET OHS OVS FSER YOE10 COE10 FSOE DRW CLAMP HS VS BUFFER CVBS0 CVBS1 CVBS2 CVBS3 CVBS4 CVBS5 CVBS6 CVBS7 C29 H15 0.1uF FSER 0.1uF 0.1uF 0.1uF C30 C64 C65 1 D1ENFS HREF CREF VREF 8 9 10 12 13 17 18 19 20 21 22 23 26 27 28 29 30 31 32 8 9 10 12 13 17 18 19 20 21 22 23 26 27 28 29 30 31 32 140 138 137 136 135 133 132 131 130 121 120 119 118 117 102 101 100 99 98 97 96 95 92 91 90 89 88 87 86 83 82 81 80 79 78 73 72 70 69 68 67 65 64 63 62 60 59 51 49 48 47 46 44 43 42 41 39 38 37 36 33 140 138 137 136 135 133 132 131 130 121 120 119 118 117 102 101 100 99 98 97 96 95 92 91 90 89 88 87 86 83 82 81 80 79 78 73 72 70 69 68 67 65 64 63 62 60 59 51 49 48 47 46 44 43 42 41 39 38 37 36 33 TMB22153AMS100 R36 1K 675MHZ HS VS HS VS DHSYNC DVSYNC DHSYNC DVSYNC SWW SWW PGM_START PGM_START PGM_OUT PGM_OUT AVOUT AVOUT SDA SCL SDA SCL DECCLK DECCLK CVBS[0..7] CVBS[0..7] VCC C22 C23 C24 C25 C26 C27 C28 PRELIMINARY INFORMATION 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 1 GND 19 GND 20 21 22 23 24 25 26 27 28 29 VDD 31 32 33 34 35 36 37 38 GND 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Preliminary Information 72 40 41 42 43 44 45 46 47 VDD 49 50 51 52 53 54 55 56 57 58 VDD 60 61 62 63 64 65 66 67 68 69 70 71 GND P1 SIMM72 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 PRELIMINARY INFORMATION COVER1 COVER0 COVER9 COVER8 COVER7 COVER6 COVER5 COVER4 COVER3 COVER2 YOVER9 YOVER8 YOVER7 YOVER6 YOVER5 YOVER4 YOVER3 YOVER2 2 3 4 5 6 7 8 9 VDD 11 12 13 14 15 16 17 18 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 YOVER1 YOVER0 7 YOVER[0..9] FSIN_CLK D1ENFS RESET\ FSER FSOE SDA SCL HS VS VCC IXPXCK IXVSYNC\ IXHSYNC\ COVER[0..9] TMB22153AMS100 Preliminary Information TMB22153AMS100 8 Y[0..9] Y[0..9] JP6A JP6B 2 JP7 MPU0 1 LOCK JP4 GY0 1 Y0 1 1 2 3 RV0 RV1 RV2 4 6 8 10 1 2 3 3 5 7 9 MPU1 MPU2 MPU3 MPU4 4 5 6 7 8 12 14 16 18 20 GY1 GY2 GY3 GY4 GY5 2 3 4 5 6 4 5 6 7 8 RV3 RV4 RV5 RV6 RV7 11 13 15 17 19 9 10 11 12 Y1 Y2 Y3 Y4 Y5 2 3 4 5 6 GY6 GY7 GY8 GY9 7 8 9 10 HEADER 10 Y6 Y7 Y8 Y9 CREF 21 23 25 27 29 RV8 RV9 BU0 BU1 BU2 9 10 11 12 7 8 9 10 HEADER 10 22 24 26 28 30 OVS OHS HREF VREF 31 33 35 37 13 14 15 16 17 13 14 15 16 17 BU3 BU4 BU5 BU6 32 34 36 38 ODD IN NTSC/PAL RGB D1 RESET\ SCL 18 19 20 21 22 23 24 HEADER 24X2 BLANK\(DAC) 39 41 43 45 47 BU7 BU8 BU9 SDA PGM_OUT 18 19 20 21 22 40 42 44 46 48 23 24 HEADER 24X2 MPU[0..4] MPU[0..4] RV[0..9] RV[0..9] BU[0..9] GY[0..9] BU[0..9] GY[0..9] OHS OHS OVS OVS SDA SDA SCL SCL RESET\ RESET\ FID_0 ODD IN HREF HREF CREF CREF VALID LOCK VREF VREF NTSC/PAL NTSC/PAL D1 D1 PGM_OUT PGM_OUT RGB RGB PRELIMINARY INFORMATION BLANK\(DAC) BLANK\(DAC) VCC FB1 R15 JP2 RBUSEN 1OHM, 1/4W C VCC VCC F BEAD R44 R16 P2 10K R17 10K SCL SDA CAS_PROGEN 4K7 4 MRESET 74F14 VCC CASCADE INIT C62 0.1uF 15-83-0064 SJ2 PGM_START RESET\ JP11 R42 4K7 U4B 3 VCC R43 10K U4A 1 2 MRESET\ 74F14 C61 PRELIMINARY INFORMATION 10.0uF/16V S1 SCL +5V SDA GND 4 3 2 1 MRST VCC R10 10K VCC 10K 10K 10K R11 R12 R13 PGM_START PGM_START RESET\ C63 0.1uF DRST\ RESET\ 1 NC NC NC NC 1 12 23 34 1 Preliminary Information 9 PROG0 PROG1 PROG2 PROG3 1 H17 1 H18 1 H19 1 H20 1 H21 1 H22 1 H23 1 H24 SCL SDA SCL 43 42 41 40 39 38 37 36 SDA H25 135MHZ H27 H28 1 H32 135MHZ 1 H26 1 1 DRST\ GRST\ PGM_IN PGM_OUT CAS_PROGEN PROG0 PROG1 PROG2 PROG3 1 H29 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 24 25 26 27 28 29 30 31 1 H30 1 VCC 135MHZ MRESET\ 10 20 21 XTAL2 XTAL1 RST EA/VPP ALE/PROG PSEN 35 33 32 H31 2 3 4 5 6 7 8 9 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 11 13 14 15 16 17 18 19 U13 AT89C55 44 PIN PLCC DRST\ S2 GRST\ GRST\ P0 P1 P2 P3 1 2 3 4 8 7 6 5 SW DIP-4 PGM_OUT PGM_OUT SCL SDA 135MHZ TMB22153AMS100 ADCLK1 U5 C37 + R18 1 VIDEO_IN VID_BUF VCC 24 220 R20 10K R21 4.75K R45 75 AN COMP/LUMA + C38 J1 LUMA 1 100uF/6.3V 100uF/6.3V 2 PRELIMINARY INFORMATION R19 75 3 1 J3 ADCLK YOVER9 YOVER8 YOVER7 YOVER6 YOVER5 YOVER4 YOVER3 YOVER2 YOVER1 YOVER0 YOVER[0..9] VCC C66 0.01uF 0.1uF 0.01uF C67 C68 VCC VCC VCC C58 0.1uF VEE C69 0.01uF VEE YOVER[0..9] 18 19 20 23 17 DEC_N SYNC CLK BP_PULSE OE_N FE-100H U6 TP34 C39 TP 0.1uF 24 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 15 14 13 12 11 10 9 8 7 6 5 S-VIDEO 4 2 C40 R22 1 VIDEO_IN VID_BUF VCC 220 0.1uF R24 10K R25 4.75K J2 CROMA 1 2 R23 75 Preliminary Information 10 18 19 20 23 17 DEC_N SYNC CLK BP_PULSE OE_N FE-100H VCC C41 0.1uF COVER9 COVER8 COVER7 COVER6 COVER5 COVER4 COVER3 COVER2 COVER1 COVER0 COVER[0..9] VCC C70 0.01uF C71 0.1uF VCC C72 0.01uF VCC C59 0.1uF VEE C73 0.01uF VEE COVER[0..9] ADCLK2 CLAMP CLAMP D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 16 15 14 13 12 11 10 9 8 7 6 5 YOE10 YOE10 E1 YEN FPGA DIS COE10 COE10 E2 CEN FPGA DIS TMB22153AMS100 GY[0..9] U7 BUFFER MASTER0 MASTER1 50 87 88 BUFFER MASTER0 MASTER1 R30 4.7K R31 4.7K R32 4.7K R33 4.7K R34 4.7K R35 4.7K GY[0..9] VCC R28 4.7K R29 4.7K S4 SWQ SWR SWS SWT SWU SWV SWW SWX E3 SELECT HILO SET VS BU[0..9] 1 PRELIMINARY INFORMATION GA0 GA1 GA2 DA0 DA1 DA2 SER HILO 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 YOVER0 YOVER1 YOVER2 YOVER3 YOVER4 YOVER5 YOVER6 YOVER7 YOVER8 YOVER9 77 78 79 80 81 82 83 84 85 86 VIDEOA_0 VIDEOA_1 VIDEOA_2 VIDEOA_3 VIDEOA_4 VIDEOA_5 VIDEOA_6 VIDEOA_7 VIDEOA_8 VIDEOA_9 G/Y_0 G/Y_1 G/Y_2 G/Y_3 G/Y_4 G/Y_5 G/Y_6 G/Y_7 G/Y_8 G/Y_9 2 1 100 99 98 97 96 95 94 93 GY0 GY1 GY2 GY3 GY4 GY5 GY6 GY7 GY8 GY9 BU[0..9] SMT SW-8 FSET H16 1 89 3 48 49 CLOCK LDV HSYNC VSYNC FSET COVER0 COVER1 COVER2 COVER3 COVER4 COVER5 COVER6 COVER7 COVER8 COVER9 66 67 68 69 70 71 72 73 74 75 VIDEOB_0 VIDEOB_1 VIDEOB_2 VIDEOB_3 VIDEOB_4 VIDEOB_5 VIDEOB_6 VIDEOB_7 VIDEOB_8 VIDEOB_9 B/CB_0 B/CB_1 B/CB_2 B/CB_3 B/CB_4 B/CB_5 B/CB_6 B/CB_7 B/CB_8 B/CB_9 15 14 13 12 11 10 9 8 7 6 BU0 BU1 BU2 BU3 BU4 BU5 BU6 BU7 BU8 BU9 RV[0..9] RV[0..9] DECCLK HS VS R/CR_0 R/CR_1 R/CR_2 R/CR_3 R/CR_4 R/CR_5 R/CR_6 R/CR_7 R/CR_8 R/CR_9 31 32 33 30 34 35 FID_0 FID_1 FID_2 AVOUT DHSYNC DVSYNC 27 26 25 24 23 22 21 20 19 18 RV0 RV1 RV2 RV3 RV4 RV5 RV6 RV7 RV8 RV9 TP10 TP11 TP12 TP13 TP14 TP15 TP TP TP TP TP TP Preliminary Information 11 SET DRST\ SWW SWT SWU SWV SCL SDA 52 51 53 54 55 56 59 58 SET RESET SER SA_0 SA_1 SA_2 SCL SDA TMC22153KHC YOVER[0..9] VCC COVER[0..9] C42 0.1uF MPU[0..7] C43 0.1uF C44 0.1uF BUFFER MASTER0 MASTER1 BUFFER MASTER0 MASTER1 FID_0 DA0 DA1 MPU0 MPU1 MPU2 MPU3 MPU4 MPU5 MPU6 MPU7 DCSB A_0 A_1 D_0 D_1 D_2 D_3 D_4 D_5 D_6 D_7 CS R/W DRW 62 63 36 37 38 41 42 43 44 45 60 61 AVOUT DHSYNC DVSYNC SWW SWW SWQ SWR SWS DCSB DA1 DA0 DRST\ DCSB DA1 DA0 DRST\ SA0 SA1 SA2 YOVER[0..9] COVER[0..9] C45 0.1uF C46 0.1uF C47 0.1uF C48 0.1uF MPU[0..7] TMB22153AMS100 SCL SDA Preliminary Information E4 SELECT PXCK4 U4E VCC 11 10 -5V 4 PR PR RGB JP8 XHE XHSYNC\ XVSYNC\ XVE JP9 RGB 2 3 D BLANK\(DAC) BLANK\(DAC) Q CLK CL Q 1 5 12 11 6 74F74 10 IXVSYNC\ E8 SELECT CL XPXCK VDD OUT 27MHz 5 Y2 C60 0.01uF VCC C31 PRELIMINARY INFORMATION 0.1uF 13 12 96 WAY EDGE CONNECTIONS FROM THE DECODER BOARD 74F14 P3A P3B P3C PXCK4 CREF OVS OHS HREF VREF ODD IN NTSC/PAL RGB XHSYNC\ XVSYNC\ XPXCK PGM_OUT LOCK D1 RESET\ SCL SDA BLANK\(DAC) RV0 RV1 RV2 RV3 RV4 RV5 RV6 RV7 RV8 RV9 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 BU0 BU1 BU2 BU3 BU4 BU5 BU6 BU7 BU8 BU9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EURO96M EURO96M EURO96M 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 VCC R26 4.75K IXPXCK VCC 135MHZ VCC JP3 D1EN R27 10K U11A D CLK Q 8 74F74 U11B Q 9 675MHZ TMB22153AMS100 DICECLK RV[0..9] RV[0..9] Y[0..9] Y[0..9] BU[0..9] BU[0..9] OHS OHS OVS OVS SDA SDA SCL SCL RESET\ RESET\ FID_0 ODD IN HREF HREF CREF CREF VALID LOCK VREF VREF NTSC/PAL NTSC/PAL D1 D1 PGM_OUT PGM_OUT IXHSYNC\ PRELIMINARY INFORMATION TMB22153AMS100 VCC C49 0.1uF IXPXCK IXPXCK E5 SELECT 1 U8A 2 ADCLK1 ADCLK1 GPXCK GPXCK 3 74F04 U8B 4 ADCLK2 ADCLK2 74F04 Preliminary Information U8C 5 6 SJ1 74F04 SELECT 9 U8D 8 DECCLK DECCLK TP16 DECCLK 74F04 U8E 11 10 DICECLK DICECLK 74F04 U8F 13 12 FSIN_CLK FSIN_CLK GHSYNC 74F04 GH E6 SELECT IXH IXHSYNC\ GVSYNC GV E7 SELECT TP17 HS TP18 VS HS VS IXVSYNC\ IXV 13 TMB22153AMS100 PRELIMINARY INFORMATION TP19 VDD P5V 1 D1 1N4004 2 D2 RED LED 1 VDDA VCC +5V +5V + C50 22uF 35V C52 0.1uF 50V + C51 0.47uF 35V C53 0.01uF 50V 2 JP5 1 2 3 HEADER 3 1 2 GND TP20 -5V VEE -5V N5V + C54 22uF 35V FB2 C56 0.1uF 50V + C55 0.47uF 35V C57 0.01uF 50V 2 D3 1N4004 1 D4 ORANGE LED F BEAD Preliminary Information UNUSED GATES G1 U4C 5 6 GND G2 GND Ground Test Points G3 GND G4 GND G5 GND 74F14 U4D 9 8 74F14 U4F 13 12 74F14 14 PRELIMINARY INFORMATION TMB22153AMS100 OUTPUT 96 way connector (male) description and notes row A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 +5v D1 or R/V [bit 0] D1 or R/V [bit 1] D1 or R/V [bit 2] D1 or R/V [bit 3] D1 or R/V [bit 4] D1 or R/V [bit 5] D1 or R/V [bit 6] D1 or R/V [bit 7] D1 or R/V [bit 8] D1 or R/V [bit 9] Comp, G/Y, or Luma [bit 0] Comp, G/Y, or Luma [bit 1] Comp, G/Y, or Luma [bit 2] Comp, G/Y, or Luma [bit 3] Comp, G/Y, or Luma [bit 4] Comp, G/Y, or Luma [bit 5] Comp, G/Y, or Luma [bit 6] Comp, G/Y, or Luma [bit 7] Comp, G/Y, or Luma [bit 8] Comp, G/Y, or Luma [bit 9] Chroma or B/U [bit 0] Chroma or B/U [bit 1] Chroma or B/U [bit 2] Chroma or B/U [bit 3] Chroma or B/U [bit 4] Chroma or B/U [bit 5] Chroma or B/U [bit 6] Chroma or B/U [bit 7] Chroma or B/U [bit 8] Chroma or B/U [bit 9] GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 +12V GND GND +5V +5V +5V GND row B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 +12V GND LOCK D1 RESET\ SCL GND SDA OE (output enable) BLANK\ (DAC) +5v GND PXCK GND PCK GND CREF GND VSYNC\ HSYNC\ HREF VREF ODD IN GND NTSC/PAL CLAMP pulse RGB row C Analog Composite/luma GND Analog chroma XEN GND XDIR XHSYNC\ XVSYNC\ XPXCK XRS [bit 3] XRS [bit 2] XRS [bit 1] XRS [bit 0] GND -5V -5V -5V GND PGM_OUT -12V -12V IE (input enable) GND Preliminary Information 15 TMB22153AMS100 PRELIMINARY INFORMATION Output Edge Connector Design notes: Signal Flow FORWARD 1 Y/Composite LPF and Clamp Circuit TMC1185 TMC2242 1 1 1 High Quality LPF High Quality LPF High Quality LPF 65-B2193-14 EPROM FPGA TMC2072 10 bit ADCs TMC1185 Chrominance BPF and Clamp Circuit Digital LPFs Decoder Input Logic 32 32 TMC3003 2:1 MUX TMC22153 Low Quality LPF Low Quality LPF Low Quality LPF TMC2242 32 32 DC Supply SW1 +5V 0V -5V SW1 SW2 Preliminary Information Signal Flow BACKWARD 1. 2. 3. 4. Boards with different revision letters may not be compatible; damage may occur if they are connected together. XPXCK is a two times pixel clock fed BACKWARD XHSYNC and XVSYNC are timing reference signals fed BACKWARD The MASTER/SLAVE signal states if a board is a MASTER or a SLAVE board. This signal is fed FORWARD. A MASTER board produces the PXCK, HSYNC, and VSYNC signals, and a SLAVE board expects to receive XPXCK, XHSYNC, XVSYNC, etc. XDIR is fed FORWARD and controls in which direction the XRS[3:0] data flows. PGM_OUT negative going signal pulse for initiating programming of down stream boards, generated once the devices on the board have been programmed. Care must be taken to ensure that multiple devices do not try to drive the RBUS at any given time. The Minimum width of PGM_OUT is 1S. The RESET pin on the output edge connector should be connected directly to the RESET pin on the input connector. A link should be used to connect any pulse to the RESET line. The MASTER/SLAVE, XDIR, PGM_OUT and RESET pins on the output edge connector should be connected to +5V through a 10k pull up resistor. The CLAMP signal is fed BACKWARD from a MASTER to a SLAVE board. The CLAMP signal should not be fed FORWARD. 5. 6. 7. 8. 9. 16 PRELIMINARY INFORMATION TMB22153AMS100 Table 4. TMB22153AMS100 Parts List Item 1 2 Qty. 1 47 Reference Designator CR1 C1, C2, C3, C4, C5, C6, C7, C8, C9, C12, C14, C15, C16, C17, C18, C21, C22, C23, C24, C25, C26, C27, C28, C29, C30, C31, C39, C40, C41, C42, C43, C44, C45, C46, C47, C48, C49, C52, C56, C58, C59, C62, C63, C64, C65, C67, C71 C10, C11 C13 C19 C20 C37, C38 C50, C54 C51, C55 C53, C57, C60, C66, C68, C69, C70, C72, C73 C61 D1, D3 D2 D4 SJ1, E1, E2, E3, E4, E5, E6, E7, E8 FB1, FB2 G1, G2, G3, G4, G5 H1, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, H18, H19, H20, H21, H22, H23, H24, H25, H26, H27, H28, H32 JP2, JP3, JP8, JP9, JP11 JP4, JP7 JP6 J1 J2 J3 L1 P1 P2 P3 R1, R2, R3, R19, R23 R4 R5, R6, R21, R25, R26 R10, R11, R12, R13, R16, R17, R20, R24, R27, R43 R15 R18, R22, R45 R28, R29, R30, R31, R32, R33, R34, R35, R42, R44 R36, R37, R38, R39, R40 SJ2 S1 17 Description 1.235 V 0.1 F 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 2 1 1 1 2 2 2 9 1 2 1 1 9 2 5 29 0.01 F 6.8 pF 150 pF 390 pF 100 uF / 6.3 V 22 F 0.47 F 0.01 F 10.0 F / 16V 1N4004 LED RED LED ORANGE SELECT F BEAD GND LOOP PTH Preliminary Information 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 5 2 1 1 1 1 1 1 1 1 5 1 5 10 1 3 10 5 1 1 HEADER2 HEADER10 HEADER24X2 BNC LUMA BNC CHROMA CON S-VIDEO INDUCTOR HEADER72X2 SIMM72 15-83-0064 EURO96M 75 OHM 3.3 KOHM 4.75 KOHM 10 KOHM 1 OHM / 1/4W C 220 OHM 4.7 KOHM 1 KOHM CASCADE INIT PUSHBUTTON MRST TMB22153AMS100 PRELIMINARY INFORMATION Item 40 41 42 Qty. 1 1 32 Reference Designator S2 S4 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11, TP12, TP13, TP14, TP15, TP16, TP17, TP18, TP19, TP20, TP21, TP22, TP23, TP24, TP25, TP26, TP27, TP28, TP29, TP30, TP31, TP34 U1 U2 U4 U5, U6 U7 U8 U9 U11 U13 Y1 Y2 Description SW DIP-4 SW DIP-8 TP 43 44 45 46 47 1 1 1 2 1 1 1 1 1 1 1 TMC2072KHC EPF10K10TC144 74F14 FE-100H TMC22153AKHC 74F04 EPC1PC8 74F74 AT89C55 44 PIN PLCC 20MHz CRYSTAL 27MHz CRYSTAL Preliminary Information 48 49 50 51 52 53 18 PRELIMINARY INFORMATION TMB22153AMS100 Notes: Preliminary Information 19 TMB22153AMS100 PRELIMINARY INFORMATION Ordering Information Product Number TMB22153AMS100 Temperature Range 25C Speed Grade 27 MHz Screening Commercial Package 4" by 5" Printed Circuit Board Package Marking TMB22153AMS100 The TMC2070P7C parallel port to R-bus board, interface cable, Raydemo software, and all relevant documentation are included in the TMB22153AMS100 purchase price. A schematic database is available in OrCADTM format, along with EPROM maps. More information on the EPLD/FPGA design is also available. Contact the factory. The TMB22153AMS100 Demonstration Board, design documentation, and software are provided as a design example for the customers of Fairchild. Fairchild makes no warranties, express, statutory, or implied regarding merchantability or fitness for a particular purpose. Preliminary Information DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 1/20/99 0.0m 002 Stock#DS70022153AMS100 (c) 1998 Fairchild Semiconductor Corporation |
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